How to Optimize a CUDA Matmul Kernel for cuBLAS-like Performance
going from naive to 94% of cuBLAS, one kernel at a time
Robert Zhang
Hi! I'm Robert, an EE student at Purdue University passionate about optimized compute systems for AI. I'm interested in the intersection of compilers, ML systems, and hardware that turn models into fast usable systems at scale. Currently exploring accelerator operator libraries, compiler-hardware codesign, and agent-based systems. Building side projects with passion. Love all things sports, nature, and jazz related.
Selected Work
Tiny-GEMM: Packed INT4 Triton GEMM for Decode-Heavy LLM Inference
Packed INT4 GEMM kernel in Triton for decode-heavy LLM inference with hardware counter attribution and a regime model for when quantization helps. Up to 3.7× speedup on A10G.
5-Stage Pipelined RISC-V CPU
Fully pipelined 5-stage RISC-V processor in SystemVerilog with hazard detection, data forwarding, and a 2-bit branch predictor. Synthesized in Cadence targeting 70 MHz.
Memory-Constrained Graph Scheduling
A scheduler for ML accelerator computation DAGs that minimizes latency while respecting tight on-chip SRAM capacity constraints. Google MLSys 2026, Track A.
Experience
Research and industry roles spanning hardware, systems, and applied AI.
Recent Writings
Fast Multidimensional Matrix Multiplication on CPU from Scratch
loop reordering, tiling, and multithreading
Pipeline Parallelism
distributed training via model partitioning
Connect
Reach me at robertzhang930@gmail.com for business inquiries or just to say hi. Connect with me on the platforms below.